Breakthrough “nanospace” technologies by the ETU «LETI» scientists

Breakthrough “nanospace” technologies by the ETU «LETI» scientists

During creating new-generation nanocircuits, ETU «LETI» scientists have developed a unique way to seal nanoporous structures by the method of molecular layering.

10.10.2017

LETI staff members have executed a number of works in cooperation with the leading European organization – Interuniversity Microelectronic Centre, IMEC (Leuven, Belgium) in the framework of researching and modifying nanolayered organic matter compositions based on rigid chain polyimides by the method of molecular liquid infusion.

During executing the Seventh Framework European Program, the project titled as “Molecular self-assembling for sealing of ultra low-k dielectrics developed for advanced nanoelectronic devices” was implemented the first time. The project was aimed at developing the method of sealing ultra low-k dielectrics, used as interlevel insulators in the new-generation nanocircuits with nanoscale layouts. The method is based on planarizing the surface and sealing nanopores without filling them with rigid chain polyimide dielectrics by the Langmiur-Blodgett technique. Svetlana Goloudina, Candidate of chemical sciences, leading scientific worker of the ETU Microtechnology and Diagnostics Centre acted as an academic advisor on behalf of ETU «LETI» in this project.

ETU «LETI» and IMEC were granted a shared US patent titled as «Method for pore sealing of porous materials using polyimide Langmuir-Blodgett film» based on the results of the conducted work.

“The Langmiur-Blodgett method is being developed in LETI for more than 20 years. A special apparatus that allows us to conduct molecular layering experiments was created at the university. Also we use standard equipment by the Finnish company “Beneq” that opened a joint lab at ETU «LETI» in 2013”

Victor Luchinin, Head of the ETU «LETI» Micro- and Nanoelectronics Department, Doctor of Engineering, professor

Advantages of the new technology for use in nanoelectronics are obvious: the resultant planarizing insulating layer meets the requirements for the maximum permissible nanoscale dielectric thickness. It does not impair the whole structure and provides the required frequency characteristics.

Through the use of the proposed method it became possible to reduce the layouts which make it possible to increase operation speed, energy efficiency and packing density of new-generation integrated circuits.